1. Field of the Invention
The present invention relates to a saturating multiplier. In one example, the present invention relates to methods and apparatus for using the saturating multiplier to implement a multiply-accumulate (MAC) unit.
2. Description of Related Art
Hardware devices such as programmable logic chips use multipliers and associated logic to perform various operations. In typical instances, multipliers handle data having a fixed width. For example, a multiplier may be a multiplier on a 32-bit processor. In this case, the multiplier is configured to perform an operation on two 32-bit operands. In some case, the product of the two 32-bit operands can be represented as a 32-bit product. However, in other instances, a 32-bit data width may not be able to represent the 32-bit product. For example, multiplication of two 32-bit numbers may yield a 64-bit product. Because the datapath of a processor may not support the 64-bit product, saturation is provided as a solution.
When saturation occurs, the 64-bit product is simply represented as the closest value presentable by a 32-bit data sequence. The saturated value can then be added to or subtracted from other values. The adding or subtracting may involve other conditions such as carry overflow.
However, mechanisms for implementing multipliers and handling saturation associated with a multiplier are limited. In some instances, the saturation condition is explicitly detected. However, explicitly detecting saturation conditions can be inefficient, particularly on programmable devices. Consequently, techniques and mechanisms are provided for more efficiently handling saturation associated with a multiplier and multiply accumulate blocks.